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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad9040a 10-bit 40 msps a/d converter features low power: 940 mw 53 db snr @ 10 mhz a in on-chip track-and-hold, reference cmos compatible 2 v p-p analog input fully characterized dynamic performance applications ultrasound medical imaging digital oscilloscopes professional video digital communications advanced television (muse decoders) instrumentation functional block diagram error correction ad9040a 10 band gap reference 6-bit adc 5-bit adc t/h t/h t/h decode logic decode logic encode a in gnd v out v ref bp ref amp array ref amp general description the ad9040a is a complete 10-bit monolithic sampling ana log- to-digital converter (adc) with on-board track-and-hold (t/h) and reference. the unit is designed for low cost, high perfor- mance applications and requires only an encode signal to achieve 40 msps sample rates with 10-bit resolution. digital inputs and outputs are cmos compatible; the analog input requires a signal of 2 v p-p amplitude. the two-step architecture used in the ad9040a is optimized to provide the best dynamic performance available while maintaining low power requirements of only 940 mw typically; maximum dissi- pation is 1.1 w at 40 msps. the signal-to-noise ratio (snr), including harmonics, is 53 db, or 8.5 enob, when sampling an analog input of 10.3 mhz at 40 msps. competitive devices perform at less than 7.5 enob and require external references and larger input signals. the ad9040a a/d converter is available in either a 28-lead pdip or a 28-lead soic package. the two models operate over a commercial temperature range of 0 c to 70 c. contact the factory regarding availability of ceramic military temperature range devices. product highlights 1. cmos compatible logic for direct interface to asics. 2. on-board track-and-hold provides excellent high frequency performance on analog inputs, critical for communications and medical imaging applications. 3. high input impedance and 2 v p-p input range reduce need for external amplifiers. 4. easy to use; no cumbersome external voltage references required, allowing denser packing of adcs for multichannel applications. 5. available in 28-lead pdip and soic packages. 6. evaluation board includes ad9040ajr, reconstruction dac, and latches. space is available near the analog input and digital outputs of the converter for additional circuits. order as part number ad9040a/pcb (schematic shown in data sheet).
rev. d e2e ad9040aespecifications (+v s = v d = +5 v; ev s = e5 v; internal reference: encode = 40.5 msps, unless otherwise noted.) test ad9040ajn/ad9040ajr parameter (conditions) temp level min typ max unit resolution 10 bits dc accuracy differential nonlinearity 25 ci 1.0 2.0 lsb full vi 2.5 lsb integral nonlinearity 25 ci 1.0 2.25 lsb full vi 2.5 lsb no missing codes full vi guaranteed gain error 25 ci 0.5 1.5 % fs full vi 2% fs gain temperature coefficient 1 full v 70 ppm/ c analog input input voltage range 25 cv 2 v p-p input offset voltage 25 ci 2 25 mv full vi 30 mv input bias current 25 ci 7 15 a full vi 25 a input resistance 25 ci 200 350 k input capacitance 25 cv 5 pf analog bandwidth 25 cv 48 mhz band gap reference output voltage full vi 2.4 2.6 v temperature coefficient 1 full v 40 ppm/ c switching performance maximum conversion rate 25 ci 40 msps minimum conversion rate 25 ci v2 10 msps aperture delay (t a )25 cv 1.9 ns aperture uncertainty (jitter) 25 cv 7 ps, rms output propagation delay (t pd ) 2 25 ci 7.5 10 12 ns full iv 6 14 ns dynamic performance 3 transient response 25 cv 25 ns overvoltage recovery time 25 cv 40 ns signal-to-noise ratio 4 f in = 2.3 mhz 25 ci 48 54 db f in = 10.3 mhz 25 ci 47 53 db signal-to-noise ratio 4 (without harmonics) f in = 2.3 mhz 25 ci 49 55 db f in = 10.3 mhz 25 ci 48 54 db signal-to-noise ratio 4, 5 f in = 2.3 mhz 25 ci 56 db f in = 10.3 mhz 25 ci 55 db signal-to-noise ratio 4, 5 (without harmonics) f in = 2.3 mhz 25 ci 57 db f in = 10.3 mhz 25 ci 56 db second harmonic distortion f in = 2.3 mhz 25 ci 56 67 dbc f in = 10.3 mhz 25 ci 56 65 dbc third harmonic distortion f in = 2.3 mhz 25 ci 57 73 dbc f in = 10.3 mhz 25 ci 57 70 dbc two-tone intermodulation 6 25 cv 62 dbc distortion rejections differential phase 25 c iii 0.15 0.5 degrees differential gain 25 c iii 0.25 1.0 %
rev. d ad9040a e3e test ad9040ajn/ad9040ajr parameter (conditions) temp level min typ max unit encode input logic 1 voltage full vi 4.0 v logic 0 voltage full vi 1.0 v logic 1 current full vi 1 a logic 0 current full vi 1 a input capacitance 25 cv 14 pf encode pulsewidth (high) (t eh ) 7 25 civ 10 100 ns encode pulsewidth (low) (t el ) 7 25 civ 10 100 ns digital outputs logic 1 voltage full vi 4.95 v logic 0 voltage full vi 0.05 v output coding offset binary power supply v d supply current full vi 13 20 ma +v s supply current full vi 89 110 ma ev s supply current full vi 87 105 ma power dissipation full vi 0.94 1.2 w power supply rejection ratio (psrr) 8 25 ci 15 mv/v notes 1 gain temperature coefficient is for a converter using internal reference; temperature coefficient is for band gap reference onl y. 2 output propagation delay (t pd ) is measured from the 50% point of the falling edge of the encode command to the min/max voltage levels of the digital outputs with 10 pf maximum loads. 3 minimum values apply to ad9040ajr only. 4 rms signal to rms noise with analog input signal 1 db below full scale at specified frequency. 5 encode = 32 msps. 6 third order intermodulation measured with analog input frequencies of 2.3 mhz and 2.4 mhz at 7 db below full scale. 7 for rated performance at 40 msps, duty cycle of encode command should be 50% 10%. 8 measured as the ratio of the change in offset voltage for a 5% change in +v s or ev s . specifications subject to change without notice. explanation of test levels test level i 100% production tested. ii 100% production tested at 25 c and sample tested at speci- fied temperatures. ac testing done on sample basis. iii sample tested only. iv parameter is guaranteed by design and characterization testing. vp arameter is a typical value only. vi all devices are 100% production tested at 25 c. 100% production tested at temperature extremes for military tem- perature devices; guaranteed by design and characterization testing for industrial devices.
rev. d e4e ad9040a absolute maximum ratings 1 v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . ev s to +v s digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +v s v ref input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +v s digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature ad9040ajn/ad9040ajr . . . . . . . . . . . . . . . . . 0 c to 70 c storage temperature . . . . . . . . . . . . . . . . . e65 c to +150 c ordering guide model temperature range package description package option ad9040ajn 0 c to 70 c 28-lead pdip n-28 ad9040ajr 0 c to 70 c 28-lead soic package r-28 ad9040ajr-reel 0 c to 70 c 28-lead soic package r-28 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9040a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. n n + 1 no. 2 no. 3 encode n ? 1 n ? 2 n ? 3 t a t eh t el t pd a in digital outputs aperture delay description symbol pulsewidth high pulsewidth low output prop delay t a t eh t el t pd 1.9ns 10ns 10ns 7.5ns 100ns 12ns min typ max 10ns 100ns figure 1. timing diagram maximum junction temperature 2 (jn/jr suffixes) . . . . 150 c lead soldering temp (10 sec) . . . . . . . . . . . . . . . . . . . . 300 c notes 1 absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances (parts soldered to board): n package (pdip): ja = 42 c/w; jc = 10 c/w. r package (soic): ja = 47 c/w; jc = 10 c/w.
rev. d ad9040a e5e pin configuration pdip and soic top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad9040a nc = no connect gnd a in ?v s gnd +v s encode nc ?v s gnd +v s gnd bp ref v ref v out or d9 (msb ) d8 d7 d6 d5 ?v s d0 (lsb) d1 d2 d3 gnd v d d4 pin function descriptions pin no. mnemonic function 1, 12, 21 ev s 5 v power supply. 2, 4, 11, 14, 22 gnd ground. 3, 10 +v s analog 5 v power supply. 5v out internal band gap voltage reference (nominally 2.5 v). 6v ref noninverting input to reference amplifier. voltage reference for adc is connected here. 7bp ref external connection for (0.1 f) reference bypass capacitor. 8n cn o connection internally. 9 encode encode clock input to adc. internal track-and-hold placed in hold mode (adc is encoding) on rising edge. 13 a in noninverting input to track-and-hold amplifier. 15 or out-of-range condition output. active high when analog input exceeds input range of adc by 1 lsb (< f s e 1 lsb or > +f s + 1 lsb). 16 d9 (msb) most significant bit of adc output; ttl/cmos compatible. 17e20 d8ed5 digital output bits of adc; ttl/cmos compatible. 23 v d digital +5 v power supply. 24e27 d4ed1 digital output bits of adc; ttl/cmos compatible. 28 d0 (lsb) least significant bit of adc output; ttl/cmos compatible. die layout and mechanical information die dimensions . . . . . . . . . 204 mils 185 mils 21 ( 1) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ev s transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,070 passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oxynitride die attach (jn/jr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . epoxy bond wire (jn/jr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold encode gnd +v s v ref v out d1 d0 (lsb) gnd +v s ?v s d9 (msb) d8 or gnd gnd a in ?v s nc nc = no connect bp ref d7 d6 d5 d4 d3 d2 dgnd ?v s +v d
rev. d e6e ad9040a definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3 db. aperture delay the delay between the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential gain the percentage of amplitude change of a small high frequency sine wave (3.58 mhz) superimposed on a low frequency signal (15.734 khz). differential nonlinearity the deviation of any code from an ideal 1 lsb step. differential phase the phase change of a small high frequency sine wave (3.58 mhz) superimposed on a low frequency signal (15.734 khz). harmonic distortion the rms value of the fundamental divided by the rms value of the harmonic. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line de termined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency tested drops by no more than 3 db below the guar- anteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between the 50% point of the falling edge of the encode command and the 1 v/4 v points of output data. overvoltage recovery time the amount of time required for the converter to recover to 10- bit accuracy after an analog input signal 150% of full scale is reduced to the full-scale range of the converter. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise ratio (snr) the ratio of the rms signal amplitude to the rms value of noise, which is defined as the sum of all other spectral components, including harmonics but excluding dc, with an analog input signal 1 db below full scale. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude to the rms value of noise, which is defined as the sum of all other spectral components, excluding the first eight harmonics and dc, with an analog input signal 1 db below full scale. transient response the time required for the converter to achieve 10-bit accuracy when a step function is applied to the analog input. two-tone intermodulation distortion (imd) rejection the ratio of the power of either of the two input signals to the power of the strongest third order imd signal. v cc v cc v cc v out v cc v ss v ss a in 1ma 1ma 1k 1k 1k 1k 2k analog input v ref gnd 6.8k r l r l 2.5k bp ref reference circuit gnd band gap output gnd d0-d9 cmos output figure 2. equivalent circuits
rev. d t ypical performance characteristicsead9040a e7e clock rate ( msps ) dissipation (w) 0.4 1 0.6 0.8 1.0 1.2 24610204060 tpc 1. power dissipation vs. clock rate clock rate ( msps ) least significant bits (lsb) 0 0 0.5 10 20 30 40 1.0 tpc 4. differential nonlinearity vs. clock rate temperature ( c ) signal-to-noise ratio (db) 40 ?35 5 45 12 5 60 ?15 25 85 ?55 65 105 55 50 45 a in = 10.3mhz encode = 32.2msps encode = 40.5msps tpc 7. snr vs. temperature frequency (mhz) harmonic distortion (dbc) ?48 1 ?53 ?58 ?63 ?68 246102 04060 ?73 signal-to-noise ratio (db) 60 42 66 48 54 100 encode = 40.5msps harmonic distortion snr tpc 2. harmonic distortion and snr vs. analog input digital output code 0 1024 896 768 640 512 384 256 128 time (ns) 0510 15 20 25 30 35 40 45 50 tpc 5. transient response frequency (mhz) dbc 8.0 16.1 0 0 ?65 encode = 32.2msps analog in = 2.3mhz snr = 56.79db snr (w/o har.) = 57.58db second harmonic = ?68.5db third harmonic = 80.7db tpc 8. fft response clock rate ( msps ) signal-to-noise ratio (db) 42 4 48 54 60 66 12 20 28 36 a in = 10.3mhz tpc 3. snr vs. clock rate time (ns) digital output code 0 1024 0510 15 20 25 30 35 40 45 50 992 960 928 96 64 32 tpc 6. transient response (expanded view) frequency (mhz) dbc 8.0 16.1 0 0 ?65 encode = 32.2msps analog in = 10.3mhz snr = 55.37db snr (w/o har.) = 56.77db second harmonic = ?63.3db third harmonic = ?75.4db tpc 9. fft response
rev. d e8e ad9040a frequency ( mhz ) dbc 2.5 5.0 0 0 ?65 encode = 40.5msps f1 in = 2.25mhz @ ?7dbfs f2 in = 2.35mhz @ ?7dbfs 2f1 ? f2 = ?69.4dbfs 2f2 ? f1 = ?69.2dbfs tpc 10. fft response frequency (mhz) dbc 10.0 20.2 0 0 ?65 encode = 40.5msps analog in = 2.3mhz snr = 55.20db snr (w/o har.) = 55.90db second harmonic = ?75.1db third harmonic = ?73.2db tpc 11. fft response frequency (mhz) dbc 10.0 20.2 0 0 ?65 encode = 40.5msps analog in = 10.3mhz snr = 53.38db snr (w/o har.) = 54.31db second harmonic = ?64.7db third harmonic = ?73.7db tpc 12. fft response theory of operation the ad9040a employs subranging architecture and digital error correction. this combination of design techniques ensures true 10-bit accuracy at the digital outputs of the converter. at the input, the analog signal is applied to a track-and-hold (t/h) that holds the analog value that is present when the unit is strobed with an encode command. the conversion process begins on the rising edge of this pulse, which should have a 50% ( 10%) duty cycle. the minimum encode rate of the ad9040a is 10 msps because of the use of three inter- nal track-and-hold devices. the held analog value of the first track-and-hold is applied to a 5-bit flash converter and a pair of internal track-and-hold de vices (shown in the functional block diagram as a single unit). the track-and-hold devices pipeline the analog signal to the ampli- fier array through a residue ladder and switching circuit while the 5-bit flash converter resolves the most significant bits (msb) of the held analog voltage. when the 5-bit flash converter has completed its cycle, its out- put activates 1 of 32 ladder switches; these in turn cause the correct residue signal to be applied to the error amplifier array. the output of the error amplifier is applied to a 6-bit flash con- verter whose output supplies the five least significant bits (lsb) of the digital output along with one bit of error correction for the 5-bit main range converter. decode logic aligns the data from the two converters and pre- sents the result as a 10-bit parallel digital word. the output stage of the ad9040a is cmos. output data are strobed on the trailing edge of the encode command. the full-scale range of the ad9040a is determined by the refer- ence voltage applied to the v ref (pin 6) input. this voltage sets the internal flash and residue ladder voltage drops; these estab- lish the value of the lsb. because of headroom restraints, the full-scale range cannot be increased by applying a higher than specified reference voltage. conversely, a lower reference volt- age will reduce the full-scale range of the converter but will also decrease its performance. an internal band gap reference volt- age of 2.5 v is provided to assure optimum performance over the operating temperature range. using the ad9040a timing the duty cycle of the encode clock for the ad9040a is critical for obtaining the rated performance of the adc. internal pulsewidths within the track-and-hold are established by the encode command pulsewidth; to ensure rated performance, the duty cycle should be held at 50%. duty cycle variations of less than 10% will cause no degradation in performance. operation at encode rates less than 10 msps is not recom- mended. the internal track-and-hold saturates, causing erroneous conversions. this track-and-hold saturation precludes clocking the ad9040a in burst mode. the 50% duty cycle must be maintained even for sample rates down to 10 msps. the ad9040a provides latched data outputs, with 2 1/2 pipe- line delays. data outputs are available one propagation delay (t pd ) after the falling edge of the encode command (see figure 1). the length of the output data lines and the loads placed on them should be minimized to reduce transients within the ad9040a; these transients can detract from the converter?s dynamic per- formance. voltage reference a stable voltage reference is required to establish the 2 v p-p range of the ad9040a. there are two options for creating this reference. the easiest and least expensive way to implement it is to use the (2.5 v) band gap voltage reference which is internal to the adc. figure 3 illustrates the connections for using the internal reference. the internal reference has 500 a of extra drive current that can be used for other circuits. ref amp band gap reference reference 2.5v ad9040a 0.1 f v out v ref ?v s bp ref figure 3. using internal reference
rev. d ad9040a e9e some applications may require greater accuracy, improved temperature performance, or adjustment of the gain (input range) of the ad9040a, which cannot be obtained by using the internal reference. for these applications, an external 2.5 v reference can be used, as shown in figure 4. the v ref input requires 5 a of drive current. ref amp band gap reference reference ad9040a v out v ref ?v s bp ref reference 0.1 f 0.1 f figure 4. using external reference in applications using multiple ad9040as, slaving the reference inputs to a single reference output will improve gain tracking among the adcs, as shown in figure 5. v out v ref ad9040a ?v s ?v s ?v s v ref ad9040a v ref 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f ad9040a bp ref bp ref bp ref figure 5. slaving multiple ad9040as to a single internal reference in the specifications table, the gain temperature coefficient parameter under dc accuracy applies to the adc when the inter- nal reference is being used. if an external reference is used, its temperature coefficient must be taken into account to deter- mine overall temperature performance. the input range can be varied by adjusting the reference voltage applied to the ad9040a. by decreasing the reference voltage, the gain can be reduced approximately 10% with no degrada- tion in performance. increasing the reference voltage increases the gain, but for proper operation, the reference voltage should not exceed 2.6 v. time-gain control adc ultrasound and sonar systems require an increase in gain versus time. this allows the system to correct for attenuation of return pulses. figure 6 shows the ad600/ad602 amplifier and the ad9040a adc configured as a time-gain control analog-to- digital converter. the control voltage ramps from e625 mv to +625 mv, permitting 40 db of gain-control range. the voltage used for gain control can be either a linear ramp or the output of a voltage-output dac, such as the ad7242. ?625mv +625mv gain control voltage ad600/ad602 a1h1 ad9040a figure 6. ultrasound/sonar time-gain control adc using x-ampa transient response figure 7 illustrates the method for evaluating adc transient performance. two synthesizers are locked in synchronization but tuned to frequencies that are slightly offset from a 2 to 1 submultiple. one synthesizer clocks a flat pulse network at a frequency of 19.9609375 mhz to provide the analog input signal; the other synthesizer output is shaped to provide a cmos 40 mhz sam- pling clock. at the output of the ad9040a, output data reflects an interleaved alias of the input pulse. the repetitive sampling allows the measurement of adc transient response as shown in the tpcs in this data sheet. ad9040a marconi 2030 synthesizer ref marconi 2030 synthesizer ref 19.9609375mhz 40mhz flat pulse network sine to cmos analog in encode output figure 7. transient response test
rev. d e10e ad9040a layout information preserving the accuracy and dynamic performance of the ad9040a requires that designers pay special attention to the layout of the printed circuit board. analog paths should be kept as short as possible and be properly terminated to avoid reflections. the analog input and reference voltage connections should be kept away from digital signal paths; this reduces the amount of digital switching noise that is capacitively coupled into the analog section. digital signal paths should also be kept short and run lengths should be matched to avoid propagation delay mismatch. the ad9040a digital out- puts should be buffered or latched close to the device (<2 cm). this prevents load transients, which may feed back into the de vice. in high speed circuits, layout of the ground is critical. a single, low impedance ground plane on the component side of the board is recommended. power supplies should be capacitively coupled to the ground plane with high quality chip capacitors to reduce noise in the circuit. multilayer boards allow designers to lay out signal traces without interrupting the ground plane and provide low impedance ground planes. in systems with dedi- cated analog and digital grounds, all grounds of the ad9040a should be connected to the analog ground plane. the power supplies of the ad9040a should be isolated from the supplies used for external devices; this reduces the amount of noise coupled into the adc. the digital 5 v connection of the device (v d , pin 23) powers the digital outputs and should be connected to the same supply as +v s (pins 3 and 10). con- necting v d to a system digital supply may couple noise into the device. sockets limit dynamic performance and are not recom- mended for use with the ad9040a. evaluation board the evaluation board for the ad9040a (ad9040a/pcb) pro- vides an easy and flexible method for evaluating the adc?s performance without (or prior to) developing a user-specific printed circuit board. the two-sided board includes a recon- struction dac and digital output interface and uses the layout and applications suggestions outlined above. it is available from analog devices at nominal cost. generous space is provided near the analog input and digital outputs to support any additional signal processing components the user may wish to add. this prototyping area includes through- holes with 100-mil centers to support a variety of component additions. input/output/supply information power supply, analog input, clock connections, and recon structed output (rc output) are identified by labels on the evalua- tion board. operation of the evaluation board should conform to the following characteristics. table i. evaluation board characteristics parameter typical unit supply current +5 v 250 ma e5.2 v 300 ma a in impedance 51 voltage range 1.0 v clock impedance 51 frequency 40 msps rc output impedance 51 voltage range 0 v to e1 v v analog input analog input signals can be fed directly into the device under test input (a in ). the a in input is terminated at the device with a 51 resistor.
rev. d ad9040a e11e figure 8. pcb top view dac reconstruction the ad9040a evaluation board provides an onboard ad9721 reconstruction dac for observing the digitized analog input signal. the ad9721 is terminated into 51 to provide a 1 v p-p signal at the output (rc output). figure 9. pcb bottom view output data the output data bits are latched with a cmos 74ac574 that drives a 40-pin connector (amp p/n 102153-9). the data and clock signals are available on the connector per the pin assignments shown on the schematic of the evaluation board (see figure 10). output data are available on the falling edge of the clock.
rev. d e12e ad9040a table ii. digital coding analog input voltage level out-of-range digital output msb . . . lsb +1.002 v positive full scale lsb + 1 1 1111111111 +1 v positive full scale full scale lsb ? 1 0 0 1111111111 1111111110 +1/2 v positive scale scale lsb 12 12 1 / /e 0 0 1100000000 1011111111 0 v bipolar zero 0 10000000000 0 01111111111 e1/2 v 12 1 12 / / scale lsb negative scale + 0 0 0100000000 0011111111 e1 v full scale lsb negative full scale + 1 0 0 0000000001 0000000000 e1.002 v negative full scale lsb ? 1 1 0000000000
rev. d ad9040a e13e +5v c7 0.1 f c8 0.1 f c9 0.1 f c10 0.1 f c11 0.1 f c12 0.1 f c18 0.1 f c14 0.1 f c15 0.1 f c16 0.1 f c17 0.1 f c13 0.1 f ?5v ?5v ?5v ?5v +5v +5v +5v gnd gnd gnd gnd gnd u2 ad9040ajr r2 51 9 10 8 u1 74hc86 d7 r16 100 u3 74ac574 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 u4 74ac574 2 3 4 5 6 7 8 9 1 11 19 18 17 16 15 14 13 12 ck oe 1d 2d 3d 4d 5d 6d 7d 8d 1q 2q 3q 4q 5q 6q 7q 8q ck oe 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q v ref v out nc a in enc ?v s ?v s ?v s +v s +v s v d gnd gnd gnd gnd gnd bp ref (msb) d9 or d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) ?5v e1 d9 d8 d6 d5 d4 d3 d2 d1 d0 r18 100 r17 100 r13 100 r15 100 r14 100 r11 100 r12 100 r9 100 r10 100 u5 ad9721br ?5v gnd ?5v gnd ?5v gnd +5v r7 2k r5 51 r6 51 c6 0.1 f c21 10 f ?5v ?5v rc output bnc j5 1 2 3 u1 74hc86 4 5 6 u1 74hc86 u1 74hc86 12 13 11 c1 0.1 f clk +5v r1 51 ain bnc j1 bnc j2 clk h1 h2 c3 10 f c2 0.1 f j7 +5v c5 10 f c4 0.1 f j8 ?5v j9 gnd h3 #4 h4 #4 h5 #4 h6 #4 h40dmc j3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clk d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 camp in ?5v gnd ?5v gnd ref out camp out ref in iout ana ret rset ?5v gnd +5v iout o it
rev. d e14e ad9040a outline dimensions 28-lead plastic dual in-line package [pdip] (n-28) dimensions shown in millimeters and (inches) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) 0.625 (15.87) 0.600 (15.24) 28 1 14 15 0.580 (14.73) 0.485 (12.32) 1.565 (39.7) 1.380 (35.1) seating plane 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.115 (2.93) 0.015 (0.39) min 0.100 (2.54) bsc 0.70 (1.77) 0.30 (0.77) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-011ab 28-lead standard small outline package [soic] wide body (r-28) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10
rev. d ad9040a e15e revision history location page 5/03?data sheet changed from rev. c to rev. d. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/02?data sheet changed from rev. b to rev. c. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
c00553e0e5/03(d) e16e

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